An operational amplifier circuit has a variety of applications in modern electronic devices. For example, the operational amplifier circuit may be used in a driver circuit for driving a display panel, such as a liquid crystal display (LCD) panel. It is common for an operational amplifier to adopt a differential pair as an input stage for receiving input signals. The linear range of the differential pair is affected by the input voltage difference of the differential pair. For example, the relation between the input voltage difference and the output current (such as the drain current in a MOSFET implemented differential pair) is linear when the input voltage difference is small. However, the relation becomes nonlinear when the input voltage difference is too large. In order to increase the linear range, a known approach is to provide larger bias current for the differential pair, which in turn results in larger power consumption.
The linear range of a differential pair is especially important for the operational amplifier circuit in a LCD driver circuit. When the input voltage difference of the differential pair exceeds the linear range, the output voltage may deviate from the desired value, and hence the image quality provided by the LCD panel is degraded. Therefore, it is an important subject in the industry to design an operational amplifier circuit with extended linear range.
FIG. 1 shows a block diagram of an example operational amplifier (OP). The operational amplifier circuit 10 includes a differential input stage circuit 101, a loading stage circuit 102, and an output stage circuit 103. The differential input stage circuit 101 receives the first input signal Vin1 and the second input signal Vin2. The differential input stage circuit 101 may be configured to amplify a voltage difference between the first input signal Vin1 and the second input signal Vin2. The loading stage circuit 102 may be configured to convert differential currents outputted by the differential input stage circuit 101 to an output signal VO. The loading stage circuit 102 may include an active load circuit (such as transistors) and/or a passive load circuit (such as resistors, capacitors, and inductors). The active load circuit may also be referred as the gain stage circuit.
The combination of the differential input stage circuit 101 and the loading stage circuit 102 may be referred as the 1st stage OP 11. The output stage circuit 103 may be referred as the 2nd stage OP 12. The voltage gain Av of the operational amplifier circuit 10 is the product of the voltage gain Av1 of the 1st stage OP 11 and the voltage gain Av2 of the 2nd stage OP 12 (Av=Av1×Av2). The voltage gain Av1 of the 1st stage OP is the transconductance Gm of the differential input stage circuit 101 multiplied by the output resistance ro of the loading stage circuit 102 (Av1=Gm×r0).
FIG. 2 shows a circuit diagram of an example differential input stage circuit. In this example the differential input stage circuit 101 of the operational amplifier circuit 11a includes a differential pair formed by two n-type metaloxidesemiconductor field-effect transistor (NMOS) transistors M01 and M02 and a current source I01. The two NMOS transistor M01 and M02 have equal gate width and equal gate length. The current value provided by the current source I01 is I. The transistor M01 receives the first input signal Vin1, and the transistor M02 receives the second input signal Vin2. The transistors M01 and M02 in the differential input stage circuit 101 operate in the saturation region. The drain currents i1 and i2 of these two transistors M01 and M02 may be represented by the following equations:
                              i          1                =                              I            2                    +                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                I                                      ⁢                          (                                                v                  id                                2                            )                        ⁢                                          1                -                                                                            (                                                                        v                          id                                                /                        2                                            )                                        2                                                                              I                      /                                              μ                        n                                                              ⁢                                          C                      ox                                        ⁢                                          W                      L                                                                                                                              (                              Eq            .                                                  ⁢            1                    ⁢          A                )                                          i          2                =                              I            2                    -                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                I                                      ⁢                          (                                                v                  id                                2                            )                        ⁢                                          1                -                                                                            (                                                                        v                          id                                                /                        2                                            )                                        2                                                                              I                      /                                              μ                        n                                                              ⁢                                          C                      ox                                        ⁢                                          W                      L                                                                                                                              (                              Eq            .                                                  ⁢            1                    ⁢          B                )            
where μn is the charge-carrier effective mobility, W is the gate width of the NMOS transistor M01, L is the gate length of the NMOS transistor M01, Cox is the gate oxide capacitance per unit area, and vid is the input voltage difference, vid=Vin1−Vin2. Based on Eq. 1A and Eq. 1B, when
                                                        v              id                        2                    ⪡                                    I                                                μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                                                    ,                            (                  Eq          .                                          ⁢          2                )            the drain currents I1 and I2 may be approximately represented as a linear relation as follows:
                              i          1                =                              I            2                    +                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                I                                      ⁢                          (                                                v                  id                                2                            )                                                          (                              Eq            .                                                  ⁢            3                    ⁢          A                )                                          i          2                =                              I            2                    -                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                I                                      ⁢                          (                                                v                  id                                2                            )                                                          (                              Eq            .                                                  ⁢            3                    ⁢          B                )            
That is, when the condition in Eq. 2 is satisfied, the relation between the drain current and the input voltage difference vid is linear. The transconductance Gm of the differential pair shown in FIG. 2 is:
                              G          m                =                                            i              1                                                      v                id                            /              2                                =                                                    μ                n                            ⁢                              C                ox                            ⁢                              W                L                            ⁢              I                                                          (                  Eq          .                                          ⁢          4                )            
FIG. 3 shows a diagram illustrating a transconductance of the differential input stage circuit shown in FIG. 2. The horizontal axis is the input voltage difference vid. The transconductance Gm is relatively stable when the input voltage difference vid is small, and hence there is a linear transfer relation between the drain current and the input voltage difference vid. When the input voltage difference vid becomes larger, the transconductance Gm decreases, and the transfer relation becomes nonlinear. When the input voltage difference vid exceeds +ΔV1 (or less than −ΔV1), the transconductance Gm becomes 0, and hence the differential pair does not work properly under such input voltage condition.